In many memory systems a memory controller or host communicates with memory dies over a bus or interface. To ensure reliable communication, the interface lines should be properly terminated at the receiving end. Termination techniques by which the termination is implemented on the die itself are referred to as On-Die Termination (ODT).
Various ODT schemes are known in the art. For example, PCT International Publication WO2012/106131, whose disclosure is incorporated herein by reference, describes local on-die termination controllers for effecting termination of a high-speed signaling links that simultaneously engage on-die termination structures within multiple integrated-circuit memory devices. The multiple memory devices are disposed on the same memory module, and/or within the same integrated-circuit package, and are coupled to the high-speed signaling link. A termination control bus is coupled to the memory devices on the module, and provides for peer-to-peer communication of termination control signals.
U.S. Patent Application Publication 2011/0314200, whose disclosure is incorporated herein by reference, describes a method by which the termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package. The on-die termination structures are coupled to the high-speed signaling link.
U.S. Patent Application Publication 2012/0206165, whose disclosure is incorporated herein by reference, describes systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module. The apparatus comprises a plurality of memory circuits, an interface circuit operable to communicate with the plurality of the memory circuits and with a memory controller, and a transmission line, which electrically couples the interface circuit to the memory controller. The interface circuit is operable to terminate the transmission line with a single termination resistance that is selected in response to resistance-setting commands sent by the memory controller.